1. Field of the Invention
This invention relates generally to the field of integrated circuit designs. More particularly, the present invention relates to automated design of integrated circuits by synchronizing asynchronous communications.
2. Description of the Related Art
Modern electrical devices typically include one or more integrated circuit (IC) chips designed to meet specific performance requirements. As integrated circuits become more complex, it becomes more desirable for logic designers to have the ability to quickly implement complex function blocks into integrated circuit designs. In addition, as applications become more complex requiring more complex processing, designers are called upon to rapidly analyze an increasing number of possible solutions. To permit easier logic design of custom or semi-custom ICs to fulfill performance constraints or circuit requirements and to aid in circuit fabrication, automated systems for design and manufacturing have been developed. For example, automated design systems using computer-aided design (CAD) are routinely used to design highly complex ICs and ICs having short life cycles such as embedded systems.
One type of CAD systems is known as a xe2x80x9clogic synthesis system.xe2x80x9d In logic synthesis systems, inputs, outputs and a high-level design description are entered into a computer using a hardware description language (HDL). Then, using a synthesis software, the computer creates a logic design that performs the function described in the HDL.
In general, short life cycle systems such as embedded systems often include one or more multiprocessors, which are used to order the tasks of an application in parallel to satisfy time constraints. Thus, in such systems, several processors may be connected in one or more ICs by communication interfaces such as data buses for synchronous transfer or communication memory (e.g., FIFO, dual port, etc.) for asynchronous transfer. However, conventional approaches have generally designed the communication interfaces in such systems in a generic way instead of optimizing them for specific applications.
By way of example, FIG. 1A illustrates a block diagram depicting an exemplary library 100 of design units. As shown, the library 100 includes design units such as processors P1 and P2 and hardware HW1 and HW2. Each of the design units in the library 100 is capable of performing assigned tasks. For example, processor P1 may be used to perform tasks T1, T2, T3, and T4 while processor P2 can perform a task T13. Similarly, hardware HW1 may perform tasks T5, T6, T7, and T8 while hardware HW2 can be used to perform tasks T9, T10, T11, and T12. Typically, the tasks T1 to T13 are provided in a library as functions.
FIG. 1B shows modeling of an application 120 using functions and design units from the library 100. In this application modeling, tasks are represented as nodes, which are connected to one another through edges as indicated by arrows. The edges indicate communication links while the tasks represent functions. The application 120 in modeled by task nodes and communication edges. Specifically, the processor P1 is assigned tasks T1, T2, T3, and T4, which are linked to the nodes of tasks T5, T6, T7, and T8, respectively, of hardware HW1 via communication edges E1, E2, E3, and E4, respectively. The hardware HW2 is assigned tasks T9, T10, T11, and T12, which are linked to the nodes of tasks T5, T6, T7, and T8, respectively via communication edges E5, E6, E7, and E8, respectively. The task T13 of processor P2 is linked to the nodes of tasks T9, T10, T11, and T12 via communication edges E9, E10, E11, and E12.
FIG. 1C is a schematic diagram depicting a scheduling of the application 120 modeled in FIG. 1B. In this schedule diagram, the assigned tasks of the design units are scheduled as a function of time. Specifically, the tasks of each of the design units are assigned a specified time duration and scheduled in sequence. For example, the tasks of the processor P1 are scheduled in sequence of T1, T2, T3, and T4 and the tasks of hardware HW1 are scheduled in the order of T5, T6, T7, and T8. Similarly, the tasks of hardware HW2 are scheduled in sequence of T9, T10, T11, and T12.
In this configuration, the communication edges that connect the task nodes in the application 120 are scheduled as either synchronous or asynchronous communications. The determination of synchronous or asynchronous communication between a transmitting unit (i.e., transmitter) and a receiving unit (i.e., receiver) is made by the availability of the receiver unit upon completion of a task by the transmitter. If the receiver is not performing a task at the completion of the task by the transmitter, the communication is characterized as synchronous. Otherwise, the communication is asynchronous. For example, communications 152, 160, 162, 164, 166, 168, and 176 are synchronous communications while communications 156, 158, 170, 172, and 174 are asynchronous communications.
The characterization of a communication as either a synchronous or an asynchronous communication affects synthesis of the application. Typically, a synchronous communication is synthesized and implemented using a bus for communication data between two or more design units. On the other hand, an asynchronous communication is generally synthesized and implemented using a first-in-first-out buffer (FIFO), dual port, or the like to store the data for synchronization.
The application schedule of FIG. 1C can be used to synthesize an architecture of a system 180 for the application 120 as shown in FIG. 1D. The system 180 includes processors P1, P2, hardware HW1, and HW2. In addition, the system includes a pair of FIFOs: FIFO1 and a FIFO2. The FIFO1 is provided between processor P1 and hardware HW1 to allow asynchronous communications. Likewise, the FIFO2 allows asynchronous communications between hardware HW2 and processor P2.
Unfortunately, however, a FIFO, in particular, and communication memory in general, typically require a larger area in an IC chip to implement than a bus. This means that a system having a FIFO or communication memory is usually more costly to implement than one having a bus. Furthermore, due to the short life cycle of embedded systems, conventional methods, in general, have not efficiently optimized the asynchronous communications to reduce cost and die area.
Thus, what is needed is a method and apparatus for efficiently implementing asynchronous communications without attendant cost and die area required in conventional techniques.
Broadly speaking, the present invention fills these needs by providing a method and apparatus for synthesizing communication support based on communication types of an application. It should be appreciated that the present invention can be implemented in numerous ways, including as a process, an apparatus, a system, a device, or a method. Several inventive embodiments of the present invention are described below.
The present invention provides a method synthesizing communication support based on communication types of an application. In this method, an application schedule is provided for the application. The application schedule describes a plurality of units for performing specified tasks and one or more communication links between the specified tasks. After receiving the application schedule, the communication type is determined for each of the communication links in the application schedule as an asynchronous communication or a synchronous communication. Then, for each of the asynchronous communications, it is determined whether each asynchronous communication can be transformed into a semi-synchronous communication that uses an interrupt and a bus to transfer data. A communication support is synthesized for the semi-synchronous communications as synchronous communications by using the interrupt and the bus. In addition, a communication support may be synthesized for the asynchronous communications that were determined not to be semi-synchronous communications.
In another embodiment, the present invention provides an integrated circuit design tool for synthesizing communication support based on communication types of an application. The integrated circuit design tool includes (a) means for providing an application schedule for the application, the application schedule having plurality of units for performing specified tasks and one or more communication paths between the specified tasks; (b) means for determining a communication type for each of the communication paths in the application schedule as an asynchronous communication or a synchronous communication; (c) means for determining, for each of the asynchronous communications, whether each asynchronous communication can be transformed into a semi-synchronous communication that uses an interrupt and a bus to transfer data; (d) means for synthesizing a first hardware support for the semi-synchronous communications as synchronous communications by using the interrupt and the bus; and (e) means for synthesizing a second hardware support for the asynchronous communications that are not semi-synchronous communications by using a communication memory.